518 Open source projects that are alternatives of or similar to Openlane

FAST-9 Accelerator for Corner Detection

Verilog Language Extension for Visual Studio

high-performance RTL simulator

Repository for the SCALE-MAMBA MPC system

The Antikernel operating system project

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

This repository is used to release the Labs of Computer Architecture Course from USTC

HW Design: A Functional Approach

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

SoC based on VexRiscv and ICE40 UP5K

The OpenPiton Platform

High throughput JPEG decoder in Verilog for FPGA

SystemVerilog compiler and language services

CDBUS Protocol and the IP Core for FPGA users

Nim cell magic for JupyterLab or Juypter Python Notebooks.

This is the main repository for all the examples for the book Practical UVM

RISC-V Cores, SoC platforms and SoCs

Opinionated garbage for your terminal. Gotta get that yolo swag.

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Qwertycoin is a decentralized peer-to-peer protocol for safe payments worldwide.

✒️ It's a minimal and light wordpress blog theme 🎨

Plugin for Figma to write RTL text

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

A full-speed device-side USB peripheral core written in Verilog.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Quasar 2.0: Chisel equivalent of SweRV-EL2

Human Resource Machine - CPU Design #HRM

Lattice iCE40: development platform for PlatformIO

FuseSoC standard core library

OOUI is a modern JavaScript UI library with strong cross-browser support. It is the standard library for MediaWiki and Wikipedia. This is a mirror from https://gerrit.wikimedia.org. Main website:

My solutions to Alteras example labs

A Docker Compose setup for Laravel projects.

Stuff from CTF contests

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Featherweight RISC-V implementation

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

冯爱民老师《计算机组成原理A》课程设计

A FPGA implementation of the NTP and NTS protocols

Realtime VGA to ASCII Art converter

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

實作《自己動手寫CPU》書上的程式碼

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

A programming language for FPGAs.

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Laravel localization package for wrapping routes in multiple locale prefixes

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

iCESugar FPGA Board (base on iCE40UP5k)

Cross EDA Abstraction and Automation

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

All open source file and project for OpenFPGAduino project

Mobile-friendly gallery carousel 🎠 with server side rendering, lazy loading, fullscreen, thumbnails, touch, mouse emulation, RTL, keyboard navigation and customisations.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

MTGJSON Documentation Front-End Application built with Vuepress 1

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

The lab schedules for EECS168 at UC Riverside

NN on FPGA