518 Open source projects that are alternatives of or similar to Openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Various HDL (Verilog) IP Cores

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Code generation tool for configuration and status registers

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

OpenROAD's unified application implementing an RTL-to-GDS Flow

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

A Hardware Construct Language

SpinalHDL - Cryptography libraries

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Test suite designed to check compliance with the SystemVerilog standard.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Haskell library for hardware description

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Haskell to VHDL/Verilog/SystemVerilog compiler

Facilitates building open source tools for working with hardware description languages (HDLs)

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Docker Development Environment for SpinalHDL

Test suite designed to check compliance with the SystemVerilog standard.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Chisel Things for OFDM

Recipe for FPGA cooking

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

32-bit Superscalar RISC-V CPU

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Video Game custom chips reverse-engineered from silicon

Virtio implementation in SystemVerilog

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Sphinx Extension which generates various types of diagrams from Verilog code.

FPGA-based JPEG-LS image compressor.

FPGA-based RISC-V CPU+SoC.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Chisel 3: A Modern Hardware Design Language

Scala based HDL

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

RISC-V CPU Core (RV32IM)

Imitate SDcard using FPGAs.

An opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)

A collection of phase locked loop (PLL) related projects

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Robotic Application Processor

A homekit firmware for a magic home RGBW controller

C++17 implementation of an AST for Verilog code generation

The OpenPiton Platform

Documenting the Lattice ECP5 bit-stream format.

Odoo (OpenERP) Right to left support for User Interface, report and frontend

DFiant: A Dataflow Hardware Descripition Language

A collection of (more or less) useful traits for PHP7.2+

Quasar 2.0: Chisel equivalent of SweRV-EL2

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Awesome ASIC design verification

Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes

Simple interface to libmagic for Ruby Programming Language

FPGA CryptoNight V7 Minner

ZX Spectrum CPLD-based clone for rubber case

Dark magic delights in Python

NetFPGA 1G infrastructure and gateware

An abstraction library for interfacing EDA tools