578 Open source projects that are alternatives of or similar to pcievhost

RISC-V CPU Core (RV32IM)

Ruby interface to IEEE 1364-2005 Verilog VPI

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

A formally verified high-level synthesis tool based on CompCert and written in Coq.

A List of Free and Open Source Hardware Verification Tools and Frameworks

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Virtual development board for HDL design

Standard Cell Library based Memory Compiler using FF/Latch cells

Revengineered ancient PDP-11 CPUs, originals and clones

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Home of the Move programming language

Trying to verify Verilog/VHDL designs with formal methods and tools

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

"Very simple but works well" Computer Vision based ID verification solution provided by LibraX.

Yet Another RISC-V Implementation

SyReNN: Symbolic Representations for Neural Networks

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

HDL symbol generator

Verify code input. You can create a verify code input.

Fully verified model checker for realtime systems

MotionBuilder Extensions Pack

NN on FPGA

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

IoT Modelling Tool is a platform which allows users to have their own devices and components modeled in order to represent and manage a physical environment.

Reads a state transition system and performs property checking

A tiny virtualization list component(gzipped 6KB), supports dynamic height: https://dwqs.github.io/react-virtual-list/

Verified, concurrent, crash-safe transaction system

Development of the CafeOBJ interpreter

Optimise your React apps by only rendering components when in proximity to the viewport.

Real-time voice-changer for voice-chat, etc. Will support many different voice-filters and features in the future. 🎵

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Neural Network Verification Software Tool

Tartan: Evaluating Modern GPU Interconnect via a Multi-GPU Benchmark Suite

Simple integration between FastAPI and cloud authentication services (AWS Cognito, Auth0, Firebase Authentication).

Vegetation Generation Tool for Houdini

An NPM package to generate captcha images that can be used in Discord bots or various other projects

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

The PHP SDK for interacting with the Yoti Platform

L1VM - a tiny virtual machine with a 64 bit core

mirror of https://git.elphel.com/Elphel/eddr3

Source code for the EpiEstim app.

验证码 && 密码 校验View（类似于支付宝、网商银行等密码校验框）

fdtd3d is an open source 1D, 2D, 3D FDTD electromagnetics solver with MPI, OpenMP and CUDA support for x86, arm, arm64 architectures

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

WAL enables programmable waveform analysis.

A modular dynamical-systems model of Ethereum's validator economics

[Deprecated] Typescript-version of the IN3 client.

Alexa like assistant in 40 lines of code

Add virtual makeup to picture of a face.

HDLBits website practices & solutions

Main repository of the Vigor NF verification project.

VATA Tree Automata Library

Bazel build rules for Verilator

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.