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RewireExperimental compiler for a subset of Haskell to VHDL
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UhdThe USRP™ Hardware Driver Repository
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SiliceSilice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
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MetacIt is metacontroller and more
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Vhdl ModeA package for Sublime Text that aids coding in the VHDL language.
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CascadeA Just-In-Time Compiler for Verilog from VMware Research
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