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OctavoVerilog FPGA Parts Library. Old Octavo soft-CPU project.
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SpinalDevDocker Development Environment for SpinalHDL
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drec-fpga-introMaterials for "Introduction to FPGA and Verilog" at MIPT DREC
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Forth CpuA Forth CPU and System on a Chip, based on the J1, written in VHDL
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vhdl-hdmi-outHDMI Out VHDL code for 7-series Xilinx FPGAs
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XrtXilinx Run Time for FPGA
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Icicle32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs
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ShuhaiShuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
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Hastlayer SdkTurning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.
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bnn-icestickBinary Neural Network on IceStick FPGA.
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Biriscv32-bit Superscalar RISC-V CPU
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EchomodsOpen source ultrasound processing modules and building blocks
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ideasRandom ideas and interesting ideas for things we hope to eventually do.
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OpenfpgaAn Open-source FPGA IP Generator
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Openwifi HwFPGA/hardware design of openwifi
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Fpga Chip8CHIP-8 console on FPGA
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ConnectalConnectal is a framework for software-driven hardware development.
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HeteroclHeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
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yahdlA programming language for FPGAs.
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TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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captouch👇 Add capacitive touch buttons to any FPGA!
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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hlscltA Vivado HLS Command Line Helper Tool
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Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
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zc pcie dmaDMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC
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Symbiflow Arch DefsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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Wbuart32A simple, basic, formally verified UART controller
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yafpgatetrisYet Another Tetris on FPGA Implementation
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AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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polyphonyPolyphony is Python based High-Level Synthesis compiler.
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Tf2An Open Source Deep Learning Inference Engine Based on FPGA
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Free TpuFree TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
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xup compute accelerationHands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
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Dnnweaver2Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
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t2spProductive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
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fpga torture🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
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Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
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LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
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tiny-tpuSmall-scale Tensor Processing Unit built on an FPGA
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AutofpgaA utility for Composing FPGA designs from Peripherals
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DaceDaCe - Data Centric Parallel Programming
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quasiSoCNo-MMU Linux capable RISC-V SoC designed to be useful.
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vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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FPGAmp720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
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