Top 7 altera open source projects

usb-jtag - Altera USB Blaster Emulation with a FX2

✭ 49

C++c assembly Makefile fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

✭ 43

VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

✭ 27

Verilog linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

hftrx

Embedded firmware for ham radio transceivers

✭ 27

c HTML tcl javascript C++VHDL zynq stm32 ham-radio sdr altera bare-metal cortex-a baremetal hamradio ssb cortex-a7 renesas cortex-a9 stm32mp1 sdr-radio rza1 rxa1l

KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

✭ 37

scala SystemVerilog tcl python assembly Makefile shell fpga intel chisel riscv chisel3 altera risc-v rv32i avalon-mm

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

✭ 59

python Vim Script shell Dockerfile productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera modelsim

fpga-docker

Tools for running FPGA vendor toolchains with Docker

✭ 54

Makefile Dockerfile shell fpga vhdl verilog xilinx altera lattice quartus

1-7 of 7 altera projects