1522 Open source projects that are alternatives of or similar to Cores

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Code generation tool for configuration and status registers

SpinalHDL - Cryptography libraries

Virtio implementation in SystemVerilog

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

FPGA-based JPEG-LS image compressor.

A full-speed device-side USB peripheral core written in Verilog.

Haskell library for hardware description

Repository for basic (and not so basic) Verilog blocks with high re-use potential

FPGA-based RISC-V CPU+SoC.

Video Game custom chips reverse-engineered from silicon

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Sphinx Extension which generates various types of diagrams from Verilog code.

Imitate SDcard using FPGAs.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Haskell to VHDL/Verilog/SystemVerilog compiler

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Scala based HDL

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Recipe for FPGA cooking

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Docker Development Environment for SpinalHDL

List of ideas for getting started with TimVideos projects

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A Hardware Construct Language

Facilitates building open source tools for working with hardware description languages (HDLs)

RISC-V Cores, SoC platforms and SoCs

MOS6581 SID chip emulator in SystemVerilog

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Lattice iCE40: development platform for PlatformIO

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Generator of verilog description for FPGA MobileNet implementation

PDP-6 Emulator

NN on FPGA

Yet Another RISC-V Implementation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Test suite designed to check compliance with the SystemVerilog standard.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Chisel Things for OFDM

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Drop In USB CDC ACM core for iCE40 FPGA

Import and export IP-XACT XML register models

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

A FPGA implementation of the NTP and NTS protocols

mirror of https://git.elphel.com/Elphel/eddr3

Homebrew game for homebrew FPGA game console

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

EVEREST: e-Versatile Research Stick for peoples

HW Design: A Functional Approach