612 Open source projects that are alternatives of or similar to VGChips

HW Design: A Functional Approach

Sphinx Extension which generates various types of diagrams from Verilog code.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Cross EDA Abstraction and Automation

Various HDL (Verilog) IP Cores

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Haskell to VHDL/Verilog/SystemVerilog compiler

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Code generation tool for configuration and status registers

Virtio implementation in SystemVerilog

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

DFiant: A Dataflow Hardware Descripition Language

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Lattice iCE40: development platform for PlatformIO

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

RISC-V Cores, SoC platforms and SoCs

Global Dark Mode for ALL apps on ANY platforms.

MOS6581 SID chip emulator in SystemVerilog

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A configurable C++ generator of pipelined Verilog FFT cores

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

shdl6800: A 6800 processor written in SpinalHDL

Wishbone controlled I2C controllers

Programmable multichannel ADPCM decoder for FPGA

Facilitates building open source tools for working with hardware description languages (HDLs)

A FPGA core for the arcade game, Rygar (1986).

A programming language for FPGAs.

This repository contains iCEBreaker examples for Amaranth HDL.

FPGA-based JPEG-LS image compressor.

Robotic Application Processor

Generator of verilog description for FPGA MobileNet implementation

PDP-6 Emulator

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Virtual development board for HDL design

SpinalHDL - Cryptography libraries

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Yet Another RISC-V Implementation

List of ideas for getting started with TimVideos projects

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Import and export IP-XACT XML register models

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Revengineered ancient PDP-11 CPUs, originals and clones

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

NN on FPGA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

FPGA CryptoNight V7 Minner

mirror of https://git.elphel.com/Elphel/eddr3

Web-based HDL diagramming tool

A FPGA implementation of the NTP and NTS protocols