342 Open source projects that are alternatives of or similar to 80211scrambler

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

🌱 Open source ecosystem for open FPGA boards

a programmable cryptographic coprocessor in verilog

The USRP™ Hardware Driver Repository

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

A (very) minimal web browser for FPGAs implemented in Verilog

MIPS CPU implemented in Verilog

tf530

An open source library for image processing on FPGA.

Scala based HDL

Open source, high performance, FPGA-based NIC

The lab schedules for EECS168 at UC Riverside

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

A demonstration showing how several components can be compsed to build a simulated spectrogram

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

related to Spartan6 FPGA

Hardware Description Languages

High Speed Analog Front End FPGA Firmware for Novena PVT1

Verilog AXI components for FPGA implementation

HDL libraries and projects

The RIFFA development repository

Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Verilator open-source SystemVerilog simulator and lint system

Verilog library for ASIC and FPGA designers

The OpenPiton Platform

1801 series ULA reverse engineering

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.

High performance motor control

KT-Link compatible buffer for the Bus Blaster v3

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)

SD card based multi-purpose cartridge for the SNES

A CPU that implementing THCO-MIPS16 instruction set.

A Just-In-Time Compiler for Verilog from VMware Research

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

This repo is for the 4618 group nember to share code.

A tiny Open POWER ISA softcore written in VHDL 2008

Fixed FCT proof for latest coq and ssreflect

SERV - The SErial RISC-V CPU

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

RISC-V Formal Verification Framework

A Lenet ASIC Accelerator targeting minimum number of cycles

mor1kx - an OpenRISC 1000 processor IP core

Verilog Ethernet components for FPGA implementation

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

A very simple VGA controller written in verilog

An open source GPU based off of the AMD Southern Islands ISA.

Verilog implementation of the SHA-512 hash function.

SDRAM controller with multiple wishbone slave ports

Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!

mystorm sram test

A small, light weight, RISC CPU soft core