143 Open source projects that are alternatives of or similar to Bladerf Wiphy

VHDL library 4 FPGAs

AXI PSRAM Controller IP for use with Digilent Nexys 4

A pipelined RISCV implementation in VHDL

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

Second version of homemade 30 MHz - 6 GHz VNA

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

A Audio Interface for the Zedboard

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

Xilinx Deep Learning IP

An implementation of original SHA-256 hash function in (RTL) VHDL

A simple RISC-V processor for use in FPGA designs.

A work-in-progress for what is to be a software-free web server for static content.

Implementations of the Simon and Speck Block Ciphers

Scala based HDL

FPGA-based HDMI ambient lighting

VUnit is a unit testing framework for VHDL/SystemVerilog

Yet Another Forth Core...

GameCube Digital AV converter

Space Invaders game implemented with VHDL

Community created parallella projects

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

GBA on FPGA

VHDL compiler and simulator

VHDL Package for Sublime Text

Arduino MIPI DSI Shield

An implementation of DisplayPort protocol for FPGAs

An abstraction library for interfacing EDA tools

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

Various projects for the Nexys4DDR board from Digilent

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

A FPGA friendly 32 bit RISC-V CPU implementation

Scripts to build and use docker images including GHDL

Library of VHDL components that are useful in larger designs.

VCD file (Value Change Dump) command line viewer

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

A list of VHDL codes implementing cryptographic algorithms

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

VHDL Samples

This repository contains synthesizable examples which use the PoC-Library.

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

VHDL-2008 Support Library

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

A JSON library implemented in VHDL.

A List of Free and Open Source Hardware Verification Tools and Frameworks

HDL symbol generator

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

An open-source VHDL library for FPGA design.

Component video modification for the C64 8-bit computer

Image Processing Toolbox in Verilog using Basys3 FPGA

VHDL synthesis (based on ghdl)

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Two RX-channel 6 GHz FMCW radar design files

This repository is the backup of XJTU-Tripler project, participating dac19 system design contest

Acorn BBC Micro on an Altera DE1 FPGA board