342 Open source projects that are alternatives of or similar to Flute

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

SystemVerilog compiler and language services

NES in Verilog

A Compiler for the Popr Language

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Bus bridges and other odds and ends

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Hardware implementation of the SHA-256 cryptographic hash function

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Connectal is a framework for software-driven hardware development.

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

Chisel 3: A Modern Hardware Design Language

BaseJump STL: A Standard Template Library for SystemVerilog

All open source file and project for OpenFPGAduino project

Verilog SDRAM memory controller

LicheeTang 蜂鸟E203 Core

FPGA-based Nintendo Entertainment System Emulator

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Recipe for FPGA cooking

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

SystemVerilog language server

Open source software for chip reverse engineering.

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Verilog version of Z-scale (deprecated)

Open source design files for the TinyFPGA B-Series boards.

Repository for the SCALE-MAMBA MPC system

Verilog Generator of Neural Net Digit Detector for FPGA

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Verilog I2C interface for FPGA implementation

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

A Verilog HDL model of the MOS 6502 CPU

iCESugar FPGA Board (base on iCE40UP5k)

SystemVerilog parser library fully complient with IEEE 1800-2017

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

FPGA/hardware design of openwifi

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

CHIP-8 console on FPGA

A simple, basic, formally verified UART controller

32-bit Superscalar RISC-V CPU

🌱 ❄️ Collection of open-source peripherals in Verilog

FPGA,Verilog,Python

All code found on nandland is here. underconstruction.gif

The USRP™ Hardware Driver FPGA Repository

PicoRV32 - A Size-Optimized RISC-V CPU

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

A Verilog implementation of DisplayPort protocol for FPGAs

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

Verilog UART

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Small footprint and configurable PCIe core

Notes on the Red Pitaya Open Source Instrument

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

一步一步写MIPS CPU

SystemVerilog to Verilog conversion