619 Open source projects that are alternatives of or similar to Fpga101 Workshop

HAL – The Hardware Analyzer

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

Change the pitch of your voice in real-time!

A refreshed Python toolbox for building complex digital hardware

A FPGA core for the arcade game, Rygar (1986).

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

C++17 implementation of an AST for Verilog code generation

IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors

A self-hosting and educational C compiler

Chisel components for FPGA projects

A (very) minimal web browser for FPGAs implemented in Verilog

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

A lightweight high performance tensor algebra framework for modern C++

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

High performance motor control

DFiant: A Dataflow Hardware Descripition Language

Yet another toy CPU.

NetFPGA 1G infrastructure and gateware

related to Spartan6 FPGA

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

FPGA-based glitcher for the Digilent Arty FPGA development board.

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

This is the base project for the Mojo. It should be used as the starting point for all projects.

Nuclei RISC-V Software Development Kit

Maxine VM: A meta-circular research VM

a programmable cryptographic coprocessor in verilog

Documenting the Xilinx 7-series bit-stream format.

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

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Galaksija computer for FPGA

TornadoVM: A practical and efficient heterogeneous programming framework for managed languages

FPGA CryptoNight V7 Minner

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

Universal utility for programming FPGA

Virtual development board for HDL design

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Drop In USB CDC ACM core for iCE40 FPGA

QKeras: a quantization deep learning library for Tensorflow Keras

ZX Spectrum CPLD-based clone for rubber case

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Verilog Ethernet components for FPGA implementation

RISC-V simulator for x86-64

⛔ DEPRECATED ⛔ HERO Software Development Kit

CMod-S6 SoC

Contains examples to start with Kactus2.

Generate UVM register model from compiled SystemRDL input

A kernel written in Rust

A scalable High-Level Synthesis framework on MLIR

RISC-V Cores, SoC platforms and SoCs

Documentatin for YatCPU

SPI master and slave for FPGA written in VHDL

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Retro Z80 computer for the Pano Logic Thin Client

G.729 Encoder