IcesugariCESugar FPGA Board (base on iCE40UP5k)
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Fpga Peripherals🌱 ❄️ Collection of open-source peripherals in Verilog
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KryonFPGA,Verilog,Python
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Ice40 PlaygroundVarious iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
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Sv ParserSystemVerilog parser library fully complient with IEEE 1800-2017
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OpenofdmSythesizable, modular Verilog implementation of 802.11 OFDM decoder.
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FpgaThe USRP™ Hardware Driver FPGA Repository
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Picorv32PicoRV32 - A Size-Optimized RISC-V CPU
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Fpg1PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.
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Scale MambaRepository for the SCALE-MAMBA MPC system
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VscaleVerilog version of Z-scale (deprecated)
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Verilog I2cVerilog I2C interface for FPGA implementation
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SimplevoutA Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
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Openwifi HwFPGA/hardware design of openwifi
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E200 opensourceThis repository hosts the project for open-source hummingbird E203 RISC processor Core.
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Fpga Chip8CHIP-8 console on FPGA
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Wbuart32A simple, basic, formally verified UART controller
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PiccoloRISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
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NandlandAll code found on nandland is here. underconstruction.gif
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Cnn Fpga使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用
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Displayport verilogA Verilog implementation of DisplayPort protocol for FPGAs
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SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
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TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
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KestrelThe Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
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SlangSystemVerilog compiler and language services
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Basejump stlBaseJump STL: A Standard Template Library for SystemVerilog
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Chisel3Chisel 3: A Modern Hardware Design Language
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PoprcA Compiler for the Popr Language
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Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
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Fpga nesFPGA-based Nintendo Entertainment System Emulator
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OpenfpgaduinoAll open source file and project for OpenFPGAduino project
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Symbiflow Arch DefsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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Wb2axipBus bridges and other odds and ends
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MetroboyMetroBoy - A playable, circuit-level simulation of an entire Game Boy
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AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
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Fpga based cnnFPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
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MilkymistSoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
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AccdnnA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
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Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Sha256Hardware implementation of the SHA-256 cryptographic hash function
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FpganesNES in Verilog
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RidecoreRIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
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SvlsSystemVerilog language server
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DegateOpen source software for chip reverse engineering.
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ConnectalConnectal is a framework for software-driven hardware development.
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Sv2vSystemVerilog to Verilog conversion
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Biriscv32-bit Superscalar RISC-V CPU
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Verilog 6502A Verilog HDL model of the MOS 6502 CPU
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Tinyfpga B SeriesOpen source design files for the TinyFPGA B-Series boards.
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Learning Nvdla NotesNVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]
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