669 Open source projects that are alternatives of or similar to LVDS-7-to-1-Serializer

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Cross EDA Abstraction and Automation

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Example designs showing different ways to use SymbiFlow toolchains.

Programmable multichannel ADPCM decoder for FPGA

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Sphinx Extension which generates various types of diagrams from Verilog code.

FPGA/hardware design of openwifi

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A mixed signal netlist language (pre-alpha)

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

FPGA 101 - Workshop materials

Virtio implementation in SystemVerilog

GPGPU microprocessor architecture

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

The Antikernel operating system project

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

CHIP-8 console on FPGA

Tools for running FPGA vendor toolchains with Docker

Docker Development Environment for SpinalHDL

A wishbone controlled scope for FPGA's

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A FPGA friendly 32 bit RISC-V CPU implementation

Code generation tool for configuration and status registers

Human Resource Machine - CPU Design #HRM

A reimplementation of a tiny stack CPU

High throughput JPEG decoder in Verilog for FPGA

MOS6581 SID chip emulator in SystemVerilog

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

A Video display simulator

Compact FPGA game console

A utility for Composing FPGA designs from Peripherals

FPGA-based RISC-V CPU+SoC.

Connectal is a framework for software-driven hardware development.

i8080 precise replica in Verilog, based on reverse engineering of real die

A programming language for FPGAs.

A MIPS CPU implemented in Verilog

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

All open source file and project for OpenFPGAduino project

Recipe for FPGA cooking

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Yet Another Tetris on FPGA Implementation

Bus bridges and other odds and ends

Verilog Generator of Neural Net Digit Detector for FPGA

LicheeTang 蜂鸟E203 Core

Must-have verilog systemverilog modules

CNN acceleration on virtex-7 FPGA with verilog HDL

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

32-bit Superscalar RISC-V CPU

Image Processing Toolbox in Verilog using Basys3 FPGA

This is a higan/Verilator co-simulation example/framework

A simple, basic, formally verified UART controller

Notes on the Red Pitaya Open Source Instrument

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Lattice iCE40: development platform for PlatformIO