322 Open source projects that are alternatives of or similar to mos6502-kansas-lava

Bus bridges and other odds and ends

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Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A curated list of awesome open source hardware design tools

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

All open source file and project for OpenFPGAduino project

CNN acceleration on virtex-7 FPGA with verilog HDL

Notes on the Red Pitaya Open Source Instrument

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)

🎯 soap - Structural Optimisation of Arithmetic Programs

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Tools for running FPGA vendor toolchains with Docker

PlutoSDR Firmware

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

Space Invaders game implemented with VHDL

Bring Deep Learning to small devices

LicheeTang 蜂鸟E203 Core

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A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

32-bit Superscalar RISC-V CPU

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

Fixed point package for Python.

Open source ultrasound processing modules and building blocks

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

An Open-source FPGA IP Generator

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

FPGA/hardware design of openwifi

SHA-256 IP core for ZedBoard (Zynq SoC)

CHIP-8 console on FPGA

Docker Development Environment for SpinalHDL

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

A Forth CPU and System on a Chip, based on the J1, written in VHDL

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Xilinx Run Time for FPGA

A simple, basic, formally verified UART controller

Polyphony is Python based High-Level Synthesis compiler.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Turning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.

Yet Another Tetris on FPGA Implementation

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

Small-scale Tensor Processing Unit built on an FPGA

8086 Microprocessor Cheat sheet with Programs

80186 compatible SystemVerilog CPU core and FPGA reference design