342 Open source projects that are alternatives of or similar to Piccolo

CHIP-8 console on FPGA

Verilog module for calculation of FFT.

iCESugar FPGA Board (base on iCE40UP5k)

A List of Free and Open Source Hardware Verification Tools and Frameworks

Verilog UART

A 32-bit Microcontroller featuring a RISC-V core

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Pano Logic G2 Reverse Engineering Project

FPGA,Verilog,Python

Light-weight RISC-V RV32IMC microcontroller core.

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

FPGA/hardware design of openwifi

Compact FPGA game console

A simple, basic, formally verified UART controller

FPGA implementation of Cellular Neural Network (CNN)

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Regression test suite for Icarus Verilog.

🌱 ❄️ Collection of open-source peripherals in Verilog

A nicer HDL.

Open source design files for the TinyFPGA B-Series boards.

Bitcoin miner for Xilinx FPGAs

All code found on nandland is here. underconstruction.gif

A single-wire bi-directional chip-to-chip interface for FPGAs

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

Homotopy theory in Coq.

PicoRV32 - A Size-Optimized RISC-V CPU

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Verilog Generator of Neural Net Digit Detector for FPGA

A Verilog implementation of DisplayPort protocol for FPGAs

Sega Genesis for MiSTer

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

Example designs showing different ways to use SymbiFlow toolchains.

Verilog I2C interface for FPGA implementation

A reimplementation of a tiny stack CPU

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Verilog version of Z-scale (deprecated)

FPGA 101 - Workshop materials

The USRP™ Hardware Driver FPGA Repository

A mixed signal netlist language (pre-alpha)

Core description files for FuseSoC

A small 6502 system with MS BASIC in ROM

Repository for the SCALE-MAMBA MPC system

A FPGA friendly 32 bit RISC-V CPU implementation

Test suite designed to check compliance with the SystemVerilog standard.

RTL, Cmodel, and testbench for NVDLA

SystemVerilog parser library fully complient with IEEE 1800-2017

A utility for Composing FPGA designs from Peripherals

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

BaseJump STL: A Standard Template Library for SystemVerilog

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Verilog SDRAM memory controller

Chisel 3: A Modern Hardware Design Language