442 Open source projects that are alternatives of or similar to Riscy Soc

Compact FPGA game console

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

FPGA-based RISC-V CPU+SoC.

List of ideas for getting started with TimVideos projects

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Yet Another RISC-V Implementation

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

LicheeTang 蜂鸟E203 Core

Featherweight RISC-V implementation

Homebrew game for homebrew FPGA game console

Simple 3-stage pipeline RISC-V processor

Small Processing Unit 32: A compact RV32I CPU written in Verilog

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

FuseSoC standard core library

Haskell to VHDL/Verilog/SystemVerilog compiler

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

A FPGA friendly 32 bit RISC-V CPU implementation

My solutions to Alteras example labs

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

FPGA/AES/LeNet/VGG16

Stuff from CTF contests

Reko is a binary decompiler.

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

Mega CD for MiSTer

Image Processing Toolbox in Verilog using Basys3 FPGA

A wishbone controlled scope for FPGA's

❄️ Visual editor for open FPGA boards

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Alphanumeric+1 shellcoding tools for RISC-V

MicroPython for K210 RISC-V, let's play with edge AI easier

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

This is the base project for the Mojo. It should be used as the starting point for all projects.

8MB FastRAM Board for the Amiga 500 & Amiga 500+

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

The 99 Traveling Salespeople Project

FPGA 101 - Workshop materials

A mixed signal netlist language (pre-alpha)

RTL, Cmodel, and testbench for NVDLA

Barerbones OSX based Verilog simulation toolchain.

CAN Protocol Controller

CNN accelerator

A MIPS CPU implemented in Verilog

Change the pitch of your voice in real-time!

FPGA-based glitcher for the Digilent Arty FPGA development board.

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

冯爱民老师《计算机组成原理A》课程设计

Galaksija computer for FPGA

Contains examples to start with Kactus2.

CoreIR Symbolic Analyzer

G.729 Encoder

collaboration on work in progress

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Realtime VGA to ASCII Art converter