94 Open source projects that are alternatives of or similar to rocc-software

Rocket Chip Generator

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

F# RISC-V Instruction Set formal specification

RISC-V Instruction Set Metadata

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

ARV: Asynchronous RISC-V Go High-level Functional Model

Nuclei RISC-V Software Development Kit

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

This repo contains the artifact for our SOSP'19 paper on Serval

Simple risc-v emulator, able to run linux, written in C.

Freedom U Software Development Kit (FUSDK)

RISC-V SystemC-TLM simulator

Shakti: development platform for PlatformIO

A RISC-V simulator

CKB's vm, based on open source RISC-V ISA

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

An unofficial reference sheet for RISC-V.

Yet another toy CPU.

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

The Gee (寂) Operating System, written in YuLang.

UNIX-like operating system written in C and C++

riscv资料、论文等

FPGA-based RISC-V CPU+SoC.

SoC based on VexRiscv and ICE40 UP5K

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

pulp_soc is the core building component of PULP based SoCs

Embedded Rust's Peripheral Access Crate for BL602 microcontrollers

Documentatin for YatCPU

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Sedna - a pure Java RISC-V emulator.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Simple RISC-V 3-stage Pipeline in Chisel

Yet Another RISC-V Implementation

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

⛔ DEPRECATED ⛔ HERO Software Development Kit

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

异步内核就像风一样快！

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

MDEPX — A BSD-style RTOS

Rust version of THU uCore OS. Linux compatible.

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

OpenEmbedded/Yocto layer for RISC-V Architecture

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

homebrew (macOS) packages for RISC-V toolchain

Jonesforth RISC-V port.

SweRV EL2 Core

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

A kernel written in Rust

RISCV SoftCPU Contest 2018

RISC-V RV32I[MAC] emulator with ELF support

bl602 serial flasher