342 Open source projects that are alternatives of or similar to Spispy

SystemVerilog compiler and language services

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

A Compiler for the Popr Language

SystemVerilog to Verilog conversion

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

一步一步写MIPS CPU

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

Open source software for chip reverse engineering.

NES in Verilog

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

FPGA-based Nintendo Entertainment System Emulator

Chisel 3: A Modern Hardware Design Language

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

All open source file and project for OpenFPGAduino project

Small footprint and configurable PCIe core

LicheeTang 蜂鸟E203 Core

Verilog SDRAM memory controller

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

BaseJump STL: A Standard Template Library for SystemVerilog

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Recipe for FPGA cooking

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

The USRP™ Hardware Driver FPGA Repository

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

A Verilog HDL model of the MOS 6502 CPU

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Verilog UART

Repository for the SCALE-MAMBA MPC system

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Open source design files for the TinyFPGA B-Series boards.

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

iCESugar FPGA Board (base on iCE40UP5k)

Verilog I2C interface for FPGA implementation

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

synthesiseable ieee 754 floating point library in verilog

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

SystemVerilog parser library fully complient with IEEE 1800-2017

A simple, basic, formally verified UART controller

Verilog Generator of Neural Net Digit Detector for FPGA

🌱 ❄️ Collection of open-source peripherals in Verilog

CHIP-8 console on FPGA

All code found on nandland is here. underconstruction.gif

32-bit Superscalar RISC-V CPU

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA,Verilog,Python

A Verilog implementation of DisplayPort protocol for FPGAs

FPGA/hardware design of openwifi

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Open source implementation of a x86 processor

A High-performance Timing Analysis Tool for VLSI Systems

Notes on the Red Pitaya Open Source Instrument

Bus bridges and other odds and ends

Hardware implementation of the SHA-256 cryptographic hash function