905 Open source projects that are alternatives of or similar to Verilog

Code generation tool for configuration and status registers

Sphinx Extension which generates various types of diagrams from Verilog code.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Haskell library for hardware description

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

FPGA-based JPEG-LS image compressor.

Cross EDA Abstraction and Automation

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

GPGPU microprocessor architecture

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Recipe for FPGA cooking

SpinalHDL - Cryptography libraries

Virtio implementation in SystemVerilog

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

All open source file and project for OpenFPGAduino project

Various HDL (Verilog) IP Cores

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A Just-In-Time Compiler for Verilog from VMware Research

FPGA-based RISC-V CPU+SoC.

Scala based HDL

Docker Development Environment for SpinalHDL

Connectal is a framework for software-driven hardware development.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Imitate SDcard using FPGAs.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

MOS6581 SID chip emulator in SystemVerilog

Test suite designed to check compliance with the SystemVerilog standard.

Generator of verilog description for FPGA MobileNet implementation

High-speed LaserDisc RF sampler

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

RISC-V CPU Core (RV32IM)

This repository contains iCEBreaker examples for Amaranth HDL.

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH

OpenROAD's unified application implementing an RTL-to-GDS Flow

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

WAL enables programmable waveform analysis.

NN on FPGA

Yet Another RISC-V Implementation

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Transient Array Radio Telescope

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

PDP-6 Emulator

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

HAL – The Hardware Analyzer

An abstraction library for interfacing EDA tools

A full-speed device-side USB peripheral core written in Verilog.

A FPGA implementation of the NTP and NTS protocols

HW Design: A Functional Approach

A configurable C++ generator of pipelined Verilog FFT cores

mirror of https://git.elphel.com/Elphel/eddr3

A low cost FPGA development board for absolute newbies

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.