319 Open source projects that are alternatives of or similar to AutoSA

Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)

MOS6581 SID chip emulator in SystemVerilog

Lattice iCE40: development platform for PlatformIO

shdl6800: A 6800 processor written in SpinalHDL

No-MMU Linux capable RISC-V SoC designed to be useful.

Dockerfile with Vivado for CI

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

This repository contains iCEBreaker examples for Amaranth HDL.

A programming language for FPGAs.

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Virtio implementation in SystemVerilog

SystemOT, yet another home brew cpu.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH

iCE40 floorplan viewer

Schematic symbol libraries for FPGAs & microcontrollers.

The Task Parallel System Composer (TaPaSCo)

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

Programmable multichannel ADPCM decoder for FPGA

HDMI Out VHDL code for 7-series Xilinx FPGAs

👇 Add capacitive touch buttons to any FPGA!

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Yet Another Tetris on FPGA Implementation

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

RISC-V Cores, SoC platforms and SoCs

OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.

FPGA Assembly (FASM) Parser and Generator

Generator of verilog description for FPGA MobileNet implementation

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Drop In USB CDC ACM core for iCE40 FPGA

This project demonstrates DSP capabilities of Terasic DE2-115

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Binary Neural Network on IceStick FPGA.

microcontroller-based FPGA / JTAG programmer

P4-14/16 Bluespec Compiler

Unofficial Yosys WebAssembly packages

hBPF = eBPF in hardware

This repo is for ECE44x (Fall2015-Spring2016)

Cross EDA Abstraction and Automation

High-speed LaserDisc RF sampler

FPGA-based JPEG-LS image compressor.

SHA-256 IP core for ZedBoard (Zynq SoC)

Kansas Lava implementation of MOS 6502 microprocessor

Sphinx Extension which generates various types of diagrams from Verilog code.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

SpinalHDL - Cryptography libraries

A Vivado HLS Command Line Helper Tool

Dockerized FPGA toolchain experiments

PDP-6 Emulator

Upduino v2 with the ice40 up5k FPGA demos

Clash implementation of the Compucolor II home computer

SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs…