A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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Rars

RARS -- RISC-V Assembler and Runtime Simulator

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Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

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Shecc

A self-hosting and educational C compiler

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Simple risc-v emulator, able to run linux, written in C.

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Dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

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Simple RISC-V 3-stage Pipeline in Chisel

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NMSIS

Nuclei Microcontroller Software Interface Standard Development Repo

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yatcpu

Yet another toy CPU.

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Lbforth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

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Meta Riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

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bx-docker

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

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ravel

A RISC-V simulator

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Rocket Chip

Rocket Chip Generator

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F# RISC-V Instruction Set formal specification

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Diosix

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

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Maxine VM: A meta-circular research VM

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platform-shakti

Shakti: development platform for PlatformIO

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SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

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Nuclei RISC-V Software Development Kit

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Riscv Boom

SonicBOOM: The Berkeley Out-of-Order Machine

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RISC-V Instruction Set Metadata

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sedna

Sedna - a pure Java RISC-V emulator.

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Jupiter

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RISC-V processor emulator written in Rust+WASM

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mdepx

MDEPX — A BSD-style RTOS

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Repository for basic (and not so basic) Verilog blocks with high re-use potential

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Test suite designed to check compliance with the SystemVerilog standard.

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Haskell library for hardware description

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Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

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OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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xv6-riscv like OS written in Rust

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A library which configures a divider for a RecyclerView.

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RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

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C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

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OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

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Mylinearlayout

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The RISC-V software tools list, as seen on riscv.org

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