601 Open source projects that are alternatives of or similar to cpu11

1801 series ULA reverse engineering

HDL symbol generator

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Video Game custom chips reverse-engineered from silicon

Cross EDA Abstraction and Automation

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

UKNCBTL is emulator of Elektronika MS 0511 (UKNC), soviet computer based on two PDP-11 compatible processors.

Virtual development board for HDL design

Test suite designed to check compliance with the SystemVerilog standard.

BKBTL emulator, Win32 version.

Java bytecode editor

i8080 precise replica in Verilog, based on reverse engineering of real die

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Facilitates building open source tools for working with hardware description languages (HDLs)

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

gdbghidra - a visual bridge between a GDB session and GHIDRA

Reverse-Engineered Tools Count-106

PDP-6 Emulator

Some Reverse Engineering Tutorials for Beginners

Sphinx Extension which generates various types of diagrams from Verilog code.

Virtio implementation in SystemVerilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Hitman Gen 1 Reverse Engineering Project

Standard Cell Library based Memory Compiler using FF/Latch cells

A formally verified high-level synthesis tool based on CompCert and written in Coq.

MT32-PI.EXE/MT32-PI.TTP/mt32-pi-ctl is a control program for the mt32-pi MIDI synthesizer available for DOS PCs, Atari ST and Amiga computers as well as modern systems running Linux and Windows.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

NN on FPGA

CTF binary exploit code

Intel 8080/Zilog Z80 assembler written in D.

Trying to verify Verilog/VHDL designs with formal methods and tools

🕸️ A comparison of mesh generators.

No description or website provided.

Useful tools for CTF competitions

OutSystems 11 product documentation

Collection of resources for Minecraft Seedcracking

FIWARE-Node-Red integration supporting NGSI-LD

A list of resources about Software Engineering Management

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Dragon Armor 3D-printable CAD files (Autodesk Fusion 360)

A python library for calculations perfomed in electronics engineering

Software engineering blog.

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

FPGA-based JPEG-LS image compressor.

Flight profile, orbit, attitude, access.

∞ Priceloop Engineering Conventions for Scala, Python, Git Workflow etc

HDLBits website practices & solutions

Sakarya Üniversitesi'nde okuduğum süre boyunca karşıma çıkan tüm ödevler, ders notları ve çıkmış sınav soruları (All the assignments, lecture notes and exams)

安卓从开发到逆向

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

ELF patching library in Python

A cross platform tool to convert images to c64 format.

socrata data-pipeline python library

My personal tutorials and notes.

A library and extension that provides objects for scientific computing in PHP.

Yet Another VHDL tool

`mllint` is a command-line utility to evaluate the technical quality of Python Machine Learning (ML) projects by means of static analysis of the project's repository.

Intentionally vulnerable Android application.