601 Open source projects that are alternatives of or similar to cpu11

socrata data-pipeline python library

Double Pendulum visualised with fetching system information in Python.

shdl6800: A 6800 processor written in SpinalHDL

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

NN on FPGA

Simple 3-stage pipeline RISC-V processor

CTF binary exploit code

MOS6581 SID chip emulator in SystemVerilog

Intel 8080/Zilog Z80 assembler written in D.

reverse HTTP proxy tunnel via secure SSH connections.

Trying to verify Verilog/VHDL designs with formal methods and tools

Fully documented and annotated source code for Angus Duggan's Elite-A on the BBC Micro

No description or website provided.

FAST-9 Accelerator for Corner Detection

🕸️ A comparison of mesh generators.

FIWARE-Node-Red integration supporting NGSI-LD

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

A list of resources about Software Engineering Management

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Dragon Armor 3D-printable CAD files (Autodesk Fusion 360)

retrohunblog

`mllint` is a command-line utility to evaluate the technical quality of Python Machine Learning (ML) projects by means of static analysis of the project's repository.

The Eight Bit Algorithmic Language for Apple II, Commodore 64 and VIC20

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

A programming language for FPGAs.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

FPGA-based JPEG-LS image compressor.

Free open-source compressor for apLib with 5-7% better ratios

Flight profile, orbit, attitude, access.

Sister product to Trifolia Workbench that has native support for FHIR resources

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

This repository helps performance testers and engineers who wants to dive into DevOps and SRE world.

Materials for the book "Python for Mechanical and Aerospace Engineering"

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

My personal tutorials and notes.

A cross platform tool to convert images to c64 format.

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A library and extension that provides objects for scientific computing in PHP.

Programmable multichannel ADPCM decoder for FPGA

Yet Another VHDL tool

A Julia Library for DC to Daylight

Intentionally vulnerable Android application.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Geocoder is a Typescript library which helps you build geo-aware applications by providing a powerful abstraction layer for geocoding manipulations

I sum up the articles of tech blogs and share that.

Create mobile applications and enhance them with native capabilities using the OutSystems native components.

Using the historical unix 2.11 BSD operating system on the PiDP-11. With examples such as cool-retro-weatherstation.

Yet Another RISC-V Implementation

SODA SDK for Apple's Swift programming language

Yet Another Tetris on FPGA Implementation

PynamoDB asynchronous plugin

SpinalHDL - Cryptography libraries

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Trifolia template/profile editor and publication tool

Julia electrical engineering package

Clash implementation of the Compucolor II home computer

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.