778 Open source projects that are alternatives of or similar to EDSAC

PDP-6 Emulator

This is a higan/Verilator co-simulation example/framework

Yet Another RISC-V Implementation

Must-have verilog systemverilog modules

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

i8080 precise replica in Verilog, based on reverse engineering of real die

LicheeTang 蜂鸟E203 Core

FPGA/hardware design of openwifi

Verilog Generator of Neural Net Digit Detector for FPGA

Cross EDA Abstraction and Automation

Lattice iCE40: development platform for PlatformIO

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

GPGPU microprocessor architecture

A utility for Composing FPGA designs from Peripherals

A simple, basic, formally verified UART controller

Connectal is a framework for software-driven hardware development.

Recipe for FPGA cooking

CHIP-8 console on FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

All open source file and project for OpenFPGAduino project

NN on FPGA

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A programming language for FPGAs.

FPGA-based JPEG-LS image compressor.

MOS6581 SID chip emulator in SystemVerilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

A Video display simulator

Compact FPGA game console

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

FPGA-based RISC-V CPU+SoC.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

The Antikernel operating system project

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Bus bridges and other odds and ends

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

32-bit Superscalar RISC-V CPU

Notes on the Red Pitaya Open Source Instrument

Tools for running FPGA vendor toolchains with Docker

Example designs showing different ways to use SymbiFlow toolchains.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Yet Another Tetris on FPGA Implementation

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Programmable multichannel ADPCM decoder for FPGA

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Sphinx Extension which generates various types of diagrams from Verilog code.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Virtio implementation in SystemVerilog

Clash implementation of the Compucolor II home computer

A reimplementation of a tiny stack CPU

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Docker Development Environment for SpinalHDL

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Generator of verilog description for FPGA MobileNet implementation