MulticompSimple custom computer on a FPGA
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Awesome HdlHardware Description Languages
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ReonvReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
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J1scA reimplementation of a tiny stack CPU
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GplgpuGPL v3 2D/3D graphics engine in verilog
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Vhdl ModeA package for Sublime Text that aids coding in the VHDL language.
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Mist BoardCore sources and tools for the MIST board
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Spi FpgaSPI master and slave for FPGA written in VHDL
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AesAES-128 hardware implementation
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ScaffoldDonjon hardware tool for circuits security evaluation
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GretaGRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.
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Cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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FlearadioDigital FM Radio Receiver for FPGA
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Parallella HwParallella board design files
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Q2727-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
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MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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NvcVHDL compiler and simulator
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Aws FpgaOfficial repository of the AWS EC2 FPGA Hardware and Software Development Kit
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RewireExperimental compiler for a subset of Haskell to VHDL
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NexyspsramAXI PSRAM Controller IP for use with Digilent Nexys 4
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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OpenrioContains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
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PatmosPatmos is a time-predictable VLIW processor, and the processor for the T-CREST project
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AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
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Fpga FftA highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
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YafcYet Another Forth Core...
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I2s Interface VhdlA simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
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VhdlVHDL Samples
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Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
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Freezing SpiceA pipelined RISCV implementation in VHDL
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Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
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Open Source Fpga Bitcoin MinerA completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
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SpinalhdlScala based HDL
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VunitVUnit is a unit testing framework for VHDL/SystemVerilog
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OphidianOphidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
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GcvideoGameCube Digital AV converter
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Pynq DlXilinx Deep Learning IP
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Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
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Sublime VhdlVHDL Package for Sublime Text
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Lxp32 CpuA lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
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TpuTPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
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GhdlVHDL 2008/93/87 simulator
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ZynqbtcA Bitcoin miner for the Zynq chip utilizing the Zedboard.
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Haddoc2Caffe to VHDL
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