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NexyspsramAXI PSRAM Controller IP for use with Digilent Nexys 4
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Open Source Fpga Bitcoin MinerA completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
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Sublime VhdlVHDL Package for Sublime Text
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VhdlVHDL Samples
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Pynq DlXilinx Deep Learning IP
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RewireExperimental compiler for a subset of Haskell to VHDL
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YafcYet Another Forth Core...
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Q2727-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
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TpuTPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
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FlearadioDigital FM Radio Receiver for FPGA
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GhdlVHDL 2008/93/87 simulator
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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Vhdl ExtrasFlexible VHDL library
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