143 Open source projects that are alternatives of or similar to Mega65 Core

Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Caffe to VHDL

GPL v3 2D/3D graphics engine in verilog

Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

Parallella board design files

SPI master and slave for FPGA written in VHDL

Hardware Description Languages

This repository is the backup of XJTU-Tripler project, participating dac19 system design contest

A tiny Open POWER ISA softcore written in VHDL 2008

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Core sources and tools for the MIST board

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Donjon hardware tool for circuits security evaluation

HAL – The Hardware Analyzer

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

Example code for the Numato Opsis board, the first HDMI2USB production board.

A simple three-stage RISC-V CPU

Cosmos OpenSSD + Hardware and Software source distribution

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Digital FM Radio Receiver for FPGA

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

VHDL 2008/93/87 simulator

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A package for Sublime Text that aids coding in the VHDL language.

List of ideas for getting started with TimVideos projects

Two RX-channel 6 GHz FMCW radar design files

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Haskell to VHDL/Verilog/SystemVerilog compiler

🔌 Hardware Abstraction Library in Python

GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Acorn BBC Micro on an Altera DE1 FPGA board

Streaming based VHDL parser.

Flexible VHDL library

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

Trying to verify Verilog/VHDL designs with formal methods and tools

A Bitcoin miner for the Zynq chip utilizing the Zedboard.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Simple custom computer on a FPGA

A simple I2C minion in VHDL

The Zylin ZPU

Simple implementation of cache using VHDL

AES-128 hardware implementation

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

VHDL for basic floating-point operations.

Cross EDA Abstraction and Automation

Repurposing existing HDL tools to help writing better code

HashVoodoo FPGA Bitcoin Miner

Component video modification for the C64 8-bit computer

VHDL library 4 FPGAs

FPGA-based HDMI ambient lighting

A List of Free and Open Source Hardware Verification Tools and Frameworks

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.