342 Open source projects that are alternatives of or similar to Piccolo

LicheeTang 蜂鸟E203 Core

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Open source software for chip reverse engineering.

All open source file and project for OpenFPGAduino project

i8080 precise replica in Verilog, based on reverse engineering of real die

Recipe for FPGA cooking

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

SystemVerilog language server

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

一步一步写MIPS CPU

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Hardware implementation of the SHA-256 cryptographic hash function

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Bus bridges and other odds and ends

NES in Verilog

SystemVerilog to Verilog conversion

Connectal is a framework for software-driven hardware development.

A Compiler for the Popr Language

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

SystemVerilog compiler and language services

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

A utility for Composing FPGA designs from Peripherals

CHIP-8 console on FPGA

iCESugar FPGA Board (base on iCE40UP5k)

Verilog UART

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

FPGA,Verilog,Python

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

FPGA/hardware design of openwifi

A simple, basic, formally verified UART controller

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

🌱 ❄️ Collection of open-source peripherals in Verilog

Open source design files for the TinyFPGA B-Series boards.

All code found on nandland is here. underconstruction.gif

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Generator of Neural Net Digit Detector for FPGA

A Verilog implementation of DisplayPort protocol for FPGAs

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

Verilog I2C interface for FPGA implementation

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Verilog version of Z-scale (deprecated)

The USRP™ Hardware Driver FPGA Repository

Core description files for FuseSoC

Repository for the SCALE-MAMBA MPC system

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog parser library fully complient with IEEE 1800-2017

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

BaseJump STL: A Standard Template Library for SystemVerilog

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Verilog SDRAM memory controller

Chisel 3: A Modern Hardware Design Language