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Forth CpuA Forth CPU and System on a Chip, based on the J1, written in VHDL
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arvARV: Asynchronous RISC-V Go High-level Functional Model
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VenusRISC-V instruction set simulator built for education
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StylecowModern CSS to all browsers
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Monolog CascadeConfigure multiple loggers and handlers in the blink of an eye
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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DegateOpen source software for chip reverse engineering.
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YodlA VHDL frontend for Yosys
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GhdlVHDL 2008/93/87 simulator
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PatmosPatmos is a time-predictable VLIW processor, and the processor for the T-CREST project
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Pynq DlXilinx Deep Learning IP
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