342 Open source projects that are alternatives of or similar to Verilog 6502

Sphinx Extension which generates various types of diagrams from Verilog code.

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Virtio implementation in SystemVerilog

Facilitates building open source tools for working with hardware description languages (HDLs)

A Hardware Construct Language

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Lattice iCE40: development platform for PlatformIO

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Programmable multichannel ADPCM decoder for FPGA

A programming language for FPGAs.

Cross EDA Abstraction and Automation

Yet Another Tetris on FPGA Implementation

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

Docker Development Environment for SpinalHDL

Tools for running FPGA vendor toolchains with Docker

A collection of debugging busses developed and presented at zipcpu.com

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

Must-have verilog systemverilog modules

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

A litecoin scrypt miner implemented with FPGA on-chip memory.

CNN acceleration on virtex-7 FPGA with verilog HDL

An open source SPI flash emulator and monitor

Open source implementation of a x86 processor

synthesiseable ieee 754 floating point library in verilog

A High-performance Timing Analysis Tool for VLSI Systems

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Small footprint and configurable PCIe core

32-bit Superscalar RISC-V CPU

Notes on the Red Pitaya Open Source Instrument