584 Open source projects that are alternatives of or similar to yafpgatetris

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

High throughput JPEG decoder in Verilog for FPGA

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Docker Development Environment for SpinalHDL

Image Processing Toolbox in Verilog using Basys3 FPGA

Notes on the Red Pitaya Open Source Instrument

A mixed signal netlist language (pre-alpha)

Recipe for FPGA cooking

Connectal is a framework for software-driven hardware development.

Must-have verilog systemverilog modules

All open source file and project for OpenFPGAduino project

HDL libraries and projects

CNN acceleration on virtex-7 FPGA with verilog HDL

❄️ Visual editor for open FPGA boards

A wishbone controlled scope for FPGA's

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog Generator of Neural Net Digit Detector for FPGA

A MIPS CPU implemented in Verilog

Bus bridges and other odds and ends

A Video display simulator

i8080 precise replica in Verilog, based on reverse engineering of real die

GPGPU microprocessor architecture

Tools for running FPGA vendor toolchains with Docker

LicheeTang 蜂鸟E203 Core

Scala based HDL

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

A small, light weight, RISC CPU soft core

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Haskell to VHDL/Verilog/SystemVerilog compiler

This is a higan/Verilator co-simulation example/framework

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

A FPGA friendly 32 bit RISC-V CPU implementation

Human Resource Machine - CPU Design #HRM

32-bit Superscalar RISC-V CPU

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

FPGA 101 - Workshop materials

Code generation tool for configuration and status registers

A reimplementation of a tiny stack CPU

The USRP™ Hardware Driver Repository

FPGA/hardware design of openwifi

Compact FPGA game console

CHIP-8 console on FPGA

FPGA-based RISC-V CPU+SoC.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A utility for Composing FPGA designs from Peripherals

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

The Antikernel operating system project

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

A simple, basic, formally verified UART controller

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Verilog to Routing -- Open Source CAD Flow for FPGA Research

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Example designs showing different ways to use SymbiFlow toolchains.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.