653 Open source projects that are alternatives of or similar to cocotb-bus

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

🎨 Reactive & Stream & Driver based UI framework build on Mobius Utils, equipped with neumorphism-derived & utility-first styles.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

PDP-6 Emulator

mirror of https://git.elphel.com/Elphel/eddr3

Bidirectional CAN-Bus to MQTT-Bridge

MOS6581 SID chip emulator in SystemVerilog

The Graphical User Interface for webpack

Modular visual interface for GDB in Python

Fast simple API for bus arrival times in Singapore.

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

NOT UP-TO-DATE ANYMORE, UNMAINTAINED. CHECK european-transport-feeds INSTEAD. List of european long-distance transport operators, available API endpoints, GTFS feeds and client modules.

HDLBits website practices & solutions

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

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Generator of verilog description for FPGA MobileNet implementation

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

LCARS, Star Trek style, HTML + CSS interface.

Simple 3-stage pipeline RISC-V processor

Reads a state transition system and performs property checking

ElvUI for World of Warcraft - Vanilla (1.12.1)

UPDATE 20210705: Adding ZeroMQ functions in to allow full-duplex comms with deep parts of the hosts' cognitive processes, and expose speech recognition background processes, visual processes, etc. ORIGINAL DESCRIPTION >>>This is a working version of the iconic Behavior Pad "Rose Graph" Interface that the Westworld Techs use to set Host Behaviora…

A user interface for the Wii U emulator, Cemu

Standard Cell Library based Memory Compiler using FF/Latch cells

Amazingly fast and simple ground control points interface. ◎

Bazel build rules for Verilator

Qt remote GUI for WeeChat.

Mainsail is the popular web interface for Klipper

AXI support for Migen/MiSoC

OSINT Threat Intel Interface - CLI for HoneyDB

HDMI Out VHDL code for 7-series Xilinx FPGAs

A JSON library implemented in VHDL.

PCIe (1.0a to 2.0) Virtual host model for verilog

Framework to work with J1939 Frames used in CAN bus in bus, car and trucks industries

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

Designs for new Base array interface primitives, used widely through scientific machine learning (SciML) and other organizations

This repository contains iCEBreaker examples for Amaranth HDL.

JavaScript library for building user interfaces with Custom Elements, Shadow DOM and React like API

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

FAST-9 Accelerator for Corner Detection

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Nuada CLI was designed to improve your development experience by using ExpressJS and Mongoose tools.

The whir.io chat server.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

kdb+ to Apache Kafka adapter, for pub/sub

Python module to interface with original Xbox hard- and software

Small Processing Unit 32: A compact RV32I CPU written in Verilog

`in` operator for go

A Hardware Construct Language

Rust language library for communication with TMUX via CLI

Yet Another RISC-V Implementation

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

Remote Dev Tool is a tool to remote control an Xbox using memory access and RPC

ARV: Asynchronous RISC-V Go High-level Functional Model

獨立無廣告巴士預報 App

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm