555 Open source projects that are alternatives of or similar to fpga-nn

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

All open source file and project for OpenFPGAduino project

The Antikernel operating system project

Small Processing Unit 32: A compact RV32I CPU written in Verilog

GPGPU microprocessor architecture

MOS6581 SID chip emulator in SystemVerilog

A simple, basic, formally verified UART controller

32-bit Superscalar RISC-V CPU

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

A reimplementation of a tiny stack CPU

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Generator of verilog description for FPGA MobileNet implementation

FPGA-based RISC-V CPU+SoC.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

FPGA-based JPEG-LS image compressor.

A utility for Composing FPGA designs from Peripherals

Verilog Generator of Neural Net Digit Detector for FPGA

Notes on the Red Pitaya Open Source Instrument

Docker Development Environment for SpinalHDL

CNN acceleration on virtex-7 FPGA with verilog HDL

Virtio implementation in SystemVerilog

A programming language for FPGAs.

SpinalHDL - Cryptography libraries

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

High throughput JPEG decoder in Verilog for FPGA

Example designs showing different ways to use SymbiFlow toolchains.

FPGA 101 - Workshop materials

A Video display simulator

Compact FPGA game console

PDP-6 Emulator

Code generation tool for configuration and status registers

Connectal is a framework for software-driven hardware development.

i8080 precise replica in Verilog, based on reverse engineering of real die

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

LicheeTang 蜂鸟E203 Core

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

A mixed signal netlist language (pre-alpha)

FPGA/hardware design of openwifi

Bus bridges and other odds and ends

Sphinx Extension which generates various types of diagrams from Verilog code.

CHIP-8 console on FPGA

Tools for running FPGA vendor toolchains with Docker

Must-have verilog systemverilog modules

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Recipe for FPGA cooking

Cross EDA Abstraction and Automation

Yet Another Tetris on FPGA Implementation

Programmable multichannel ADPCM decoder for FPGA

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

A wishbone controlled scope for FPGA's

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Lattice iCE40: development platform for PlatformIO

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools