OpenrioContains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
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PatmosPatmos is a time-predictable VLIW processor, and the processor for the T-CREST project
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AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
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Zedboard audioA Audio Interface for the Zedboard
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Pynq DlXilinx Deep Learning IP
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I2s Interface VhdlA simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
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NeppielightFPGA-based HDMI ambient lighting
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Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
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Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
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Hardh264A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
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SpinalhdlScala based HDL
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YafcYet Another Forth Core...
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VunitVUnit is a unit testing framework for VHDL/SystemVerilog
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FpgbaGBA on FPGA
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GcvideoGameCube Digital AV converter
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Vhdl libLibrary of VHDL components that are useful in larger designs.
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Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
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Sublime VhdlVHDL Package for Sublime Text
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NvcVHDL compiler and simulator
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Dsi ShieldArduino MIPI DSI Shield
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EdalizeAn abstraction library for interfacing EDA tools
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PotatoA simple RISC-V processor for use in FPGA designs.
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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SmartVHDLSublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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dockerScripts to build and use docker images including GHDL
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Fpga FftA highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
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vcdVCD file (Value Change Dump) command line viewer
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CryptoHDLA list of VHDL codes implementing cryptographic algorithms
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VhdlVHDL Samples
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mathUseful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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PoC-ExamplesThis repository contains synthesizable examples which use the PoC-Library.
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Open Source Fpga Bitcoin MinerA completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
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fphdlVHDL-2008 Support Library
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Vna2Second version of homemade 30 MHz - 6 GHz VNA
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JSON-for-VHDLA JSON library implemented in VHDL.
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OphidianOphidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
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symbolatorHDL symbol generator
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YodlA VHDL frontend for Yosys
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noasicAn open-source VHDL library for FPGA design.
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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yavhdlYet Another VHDL tool
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Hdl4fpgaVHDL library 4 FPGAs
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Lxp32 CpuA lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
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UvvmUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
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DegateOpen source software for chip reverse engineering.
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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Neo430A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
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TpuTPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
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