752 Open source projects that are alternatives of or similar to Icezum

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

Homebrew game for homebrew FPGA game console

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Wishbone controlled I2C controllers

Scala based HDL

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

This is a higan/Verilator co-simulation example/framework

Image Processing Toolbox in Verilog using Basys3 FPGA

A configurable C++ generator of pipelined Verilog FFT cores

Repository for basic (and not so basic) Verilog blocks with high re-use potential

A wishbone controlled scope for FPGA's

A FPGA friendly 32 bit RISC-V CPU implementation

Human Resource Machine - CPU Design #HRM

List of ideas for getting started with TimVideos projects

A reimplementation of a tiny stack CPU

High throughput JPEG decoder in Verilog for FPGA

The Antikernel operating system project

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

A utility for Composing FPGA designs from Peripherals

GPGPU microprocessor architecture

Connectal is a framework for software-driven hardware development.

A Video display simulator

A simple, basic, formally verified UART controller

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

The OpenPiton Platform

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Recipe for FPGA cooking

Bus bridges and other odds and ends

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Notes on the Red Pitaya Open Source Instrument

Verilog Generator of Neural Net Digit Detector for FPGA

Must-have verilog systemverilog modules

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Docker Development Environment for SpinalHDL

mirror of https://git.elphel.com/Elphel/eddr3

A programming language for FPGAs.

Lattice iCE40: development platform for PlatformIO

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Sphinx Extension which generates various types of diagrams from Verilog code.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Virtio implementation in SystemVerilog

PDP-6 Emulator

FPGA-based JPEG-LS image compressor.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Open source ultrasound processing modules and building blocks

All open source file and project for OpenFPGAduino project

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Yet Another RISC-V Implementation

RISC-V CPU Core (RV32IM)

Haskell library for hardware description

RISCV SoftCPU Contest 2018