Vhdl ModeA package for Sublime Text that aids coding in the VHDL language.
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MulticompSimple custom computer on a FPGA
Stars: ✭ 8 (-92.98%)
J1scA reimplementation of a tiny stack CPU
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ZynqbtcA Bitcoin miner for the Zynq chip utilizing the Zedboard.
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Fpga BbcAcorn BBC Micro on an Altera DE1 FPGA board
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Xjtu TriplerThis repository is the backup of XJTU-Tripler project, participating dac19 system design contest
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Haddoc2Caffe to VHDL
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ScaffoldDonjon hardware tool for circuits security evaluation
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GretaGRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology.
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FlearadioDigital FM Radio Receiver for FPGA
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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AesAES-128 hardware implementation
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Q2727-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
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TpuTPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
Stars: ✭ 91 (-20.18%)
Spi FpgaSPI master and slave for FPGA written in VHDL
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Fpga FftA highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
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Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
Stars: ✭ 762 (+568.42%)
PatmosPatmos is a time-predictable VLIW processor, and the processor for the T-CREST project
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VhdlVHDL Samples
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Open Source Fpga Bitcoin MinerA completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
Stars: ✭ 989 (+767.54%)
Pynq DlXilinx Deep Learning IP
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OphidianOphidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
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Nexys4ddrVarious projects for the Nexys4DDR board from Digilent
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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Lxp32 CpuA lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
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YodlA VHDL frontend for Yosys
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YafcYet Another Forth Core...
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RewireExperimental compiler for a subset of Haskell to VHDL
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FpgbaGBA on FPGA
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NexyspsramAXI PSRAM Controller IP for use with Digilent Nexys 4
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OpenrioContains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
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Ethernet macTri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
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AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
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Sublime VhdlVHDL Package for Sublime Text
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Zedboard audioA Audio Interface for the Zedboard
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Stars: ✭ 106 (-7.02%)
I2s Interface VhdlA simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
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Aws FpgaOfficial repository of the AWS EC2 FPGA Hardware and Software Development Kit
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Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
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Freezing SpiceA pipelined RISCV implementation in VHDL
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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Artix 7 Hdmi ProcessingReceiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
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Cosmos Plus OpenssdCosmos OpenSSD + Hardware and Software source distribution
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Hdl checkerRepurposing existing HDL tools to help writing better code
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GhdlVHDL 2008/93/87 simulator
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ReonvReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
Stars: ✭ 47 (-58.77%)