143 Open source projects that are alternatives of or similar to Neppielight

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

Community created parallella projects

VHDL Samples

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A List of Free and Open Source Hardware Verification Tools and Frameworks

VHDL compiler and simulator

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

Arduino MIPI DSI Shield

Xilinx Deep Learning IP

An abstraction library for interfacing EDA tools

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

Various projects for the Nexys4DDR board from Digilent

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

Image Processing Toolbox in Verilog using Basys3 FPGA

Scripts to build and use docker images including GHDL

Implementations of the Simon and Speck Block Ciphers

VCD file (Value Change Dump) command line viewer

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

A list of VHDL codes implementing cryptographic algorithms

A VHDL frontend for Yosys

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

VHDL-Mips-Pipeline-Microprocessor

This repository contains synthesizable examples which use the PoC-Library.

Yet Another Forth Core...

VHDL-2008 Support Library

Experimental compiler for a subset of Haskell to VHDL

A JSON library implemented in VHDL.

GBA on FPGA

HDL symbol generator

AXI PSRAM Controller IP for use with Digilent Nexys 4

An open-source VHDL library for FPGA design.

Yet Another VHDL tool

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

OpenN@S: Open-source software to NAS automatic VHDL code generation

Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL

Virtual development board for HDL design

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

SpinalHDL - Cryptography libraries

VHDL Package for Sublime Text

HDMI Out VHDL code for 7-series Xilinx FPGAs

A Audio Interface for the Zedboard

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

👇 Add capacitive touch buttons to any FPGA!

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

@elahe-dastan / @1995parham training and testing repository 📚 🤓

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Interface for MSX to Connect and use Raspberry Pi resources

An implementation of original SHA-256 hash function in (RTL) VHDL

Docker Development Environment for SpinalHDL

A pipelined RISCV implementation in VHDL

A work-in-progress for what is to be a software-free web server for static content.

Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA

Cosmos OpenSSD + Hardware and Software source distribution

Repurposing existing HDL tools to help writing better code

VHDL 2008/93/87 simulator

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

GPL v3 2D/3D graphics engine in verilog