316 Open source projects that are alternatives of or similar to Nmigen

QKeras: a quantization deep learning library for Tensorflow Keras

An example of how to use the Xilinx ISE toolchain from the command line

An open source library for image processing on FPGA.

RISC-V CPU Core (RV32IM)

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

Brevitas: quantization-aware training in PyTorch

usb-jtag - Altera USB Blaster Emulation with a FX2

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Common elements for FPGA Design (FIFOs, RAMs, etc.)

PCI Express DIY hacking toolkit for Xilinx SP605

The OpenPiton Platform

Robotic Application Processor

🌱 Open source ecosystem for open FPGA boards

An abstraction library for interfacing EDA tools

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

CMod-S6 SoC

中文版 Parallel Programming for FPGAs

An experiment for building gateware for the axiom micro / beta using nmigen and yosys

RISC-V Cores, SoC platforms and SoCs

Library of approximate arithmetic circuits

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

A collection of phase locked loop (PLL) related projects

Repository for basic (and not so basic) Verilog blocks with high re-use potential

A lightweight high performance tensor algebra framework for modern C++

DFiant: A Dataflow Hardware Descripition Language

A refreshed Python toolbox for building complex digital hardware

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Various HDL (Verilog) IP Cores

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

Universal utility for programming FPGA

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Imitate SDcard using FPGAs.

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Haskell library for hardware description

VUnit is a unit testing framework for VHDL/SystemVerilog

A simple three-stage RISC-V CPU

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Fast inference of Boosted Decision Trees in FPGAs

Documenting the Xilinx 7-series bit-stream format.

PYNQ Composabe Overlays

SDAccel Examples

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

Homebrew game for homebrew FPGA game console

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Video Game custom chips reverse-engineered from silicon

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

A FPGA core for the arcade game, Rygar (1986).

A Just-In-Time Compiler for Verilog from VMware Research

HAL – The Hardware Analyzer

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

TornadoVM: A practical and efficient heterogeneous programming framework for managed languages

Machine learning in FPGAs using HLS

SweRV EH1 core

Dataflow compiler for QNN inference on FPGAs