OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
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RggenCode generation tool for configuration and status registers
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Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
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sv-testsTest suite designed to check compliance with the SystemVerilog standard.
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virtioVirtio implementation in SystemVerilog
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Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
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xedaCross EDA Abstraction and Automation
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OpentimerA High-performance Timing Analysis Tool for VLSI Systems
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SpinalhdlScala based HDL
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blarneyHaskell library for hardware description
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LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
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Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
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SpinalDevDocker Development Environment for SpinalHDL
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walWAL enables programmable waveform analysis.
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EdalizeAn abstraction library for interfacing EDA tools
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ofdmChisel Things for OFDM
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OpenlaneOpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
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Skywater PdkOpen source process design kit for usage with SkyWater Technology Foundry's 130nm node.
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gdsfactoryPython package to generate GDS layouts.
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hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
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Chisel3Chisel 3: A Modern Hardware Design Language
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cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
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Edavizedaviz - Python library for Exploratory Data Analysis and Visualization in Jupyter Notebook or Jupyter Lab
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svutSVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
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100 Days Of Ml CodeA day to day plan for this challenge. Covers both theoritical and practical aspects
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Rath自动化数据探索分析和智能可视化设计应用. Automatic insights discovery and visualization for data analysis.
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vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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ScattertextBeautiful visualizations of how language differs among document types.
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yahdlA programming language for FPGAs.
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padringA padring generator for ASICs
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SweetvizVisualize and compare datasets, target values and associations, with one line of code.
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