779 Open source projects that are alternatives of or similar to pdp6

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

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Implementation of a Tensor Processing Unit for embedded systems and the IoT.

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GPGPU microprocessor architecture

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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

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CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

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SpinalHDL - Cryptography libraries

FPGA-based RISC-V CPU+SoC.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

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CNN acceleration on virtex-7 FPGA with verilog HDL

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Tools for running FPGA vendor toolchains with Docker

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

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High throughput JPEG decoder in Verilog for FPGA

The Antikernel operating system project

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Compact FPGA game console

FPGA-based JPEG-LS image compressor.

Code generation tool for configuration and status registers

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i8080 precise replica in Verilog, based on reverse engineering of real die

A simple, basic, formally verified UART controller

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

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Recipe for FPGA cooking

A mixed signal netlist language (pre-alpha)

32-bit Superscalar RISC-V CPU

Notes on the Red Pitaya Open Source Instrument

Must-have verilog systemverilog modules

Verilog Generator of Neural Net Digit Detector for FPGA

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Docker Development Environment for SpinalHDL

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

FPGA/hardware design of openwifi

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Programmable multichannel ADPCM decoder for FPGA

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Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A wishbone controlled scope for FPGA's

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Bus bridges and other odds and ends

Cross EDA Abstraction and Automation