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Vm80ai8080 precise replica in Verilog, based on reverse engineering of real die
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Archexp浙江大学计算机体系结构课程实验
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Wujian100 openIC design and development should be faster,simpler and more reliable
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SvlsSystemVerilog language server
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LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
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CpuA very primitive but hopefully self-educational CPU in Verilog
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FpganesNES in Verilog
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AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
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Spatial LangSpatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
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ConnectalConnectal is a framework for software-driven hardware development.
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VgasimA Video display simulator
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Symbiflow Arch DefsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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Oldland CpuOldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
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VsdflowVSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
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Hardware CnnA convolutional neural network implemented in hardware (verilog)
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HomotopyHomotopy theory in Coq.
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Hdl checkerRepurposing existing HDL tools to help writing better code
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Wbuart32A simple, basic, formally verified UART controller
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Fft Dit FpgaVerilog module for calculation of FFT.
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MriscvA 32-bit Microcontroller featuring a RISC-V core
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SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
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Panologic G2Pano Logic G2 Reverse Engineering Project
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Fpga Peripherals🌱 ❄️ Collection of open-source peripherals in Verilog
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KamikazeLight-weight RISC-V RV32IMC microcontroller core.
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VscaleVerilog version of Z-scale (deprecated)
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IcesugariCESugar FPGA Board (base on iCE40UP5k)
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Orpsoc CoresCore description files for FuseSoC
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Fpga CnnFPGA implementation of Cellular Neural Network (CNN)
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IvtestRegression test suite for Icarus Verilog.
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Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
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HoodlumA nicer HDL.
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OpenofdmSythesizable, modular Verilog implementation of 802.11 OFDM decoder.
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AutofpgaA utility for Composing FPGA designs from Peripherals
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PonylinkA single-wire bi-directional chip-to-chip interface for FPGAs
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Picorv32PicoRV32 - A Size-Optimized RISC-V CPU
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ReplaceRePlAce global placement tool
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Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
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OpenfpgaduinoAll open source file and project for OpenFPGAduino project
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Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
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A2o Stars: ✭ 107 (-23.02%)