341 Open source projects that are alternatives of or similar to Solutions-to-HDLbits-Verilog-sets

HDLBits website practices & solutions

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

32-bit Superscalar RISC-V CPU

FPGA/hardware design of openwifi

synthesiseable ieee 754 floating point library in verilog

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Programmable multichannel ADPCM decoder for FPGA

A collection of debugging busses developed and presented at zipcpu.com

Verilog UART

Verilog I2C interface for FPGA implementation

An open source SPI flash emulator and monitor

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A Verilog HDL model of the MOS 6502 CPU

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Verilog Generator of Neural Net Digit Detector for FPGA

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

The USRP™ Hardware Driver FPGA Repository

Docker Development Environment for SpinalHDL

Open source design files for the TinyFPGA B-Series boards.

Cross EDA Abstraction and Automation

Must-have verilog systemverilog modules

SystemVerilog parser library fully complient with IEEE 1800-2017

CHIP-8 console on FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Open source implementation of a x86 processor

Lattice iCE40: development platform for PlatformIO

A High-performance Timing Analysis Tool for VLSI Systems

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Small footprint and configurable PCIe core

A Hardware Construct Language

Notes on the Red Pitaya Open Source Instrument

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

FPGA-based Nintendo Entertainment System Emulator

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

BaseJump STL: A Standard Template Library for SystemVerilog

Virtio implementation in SystemVerilog

Bus bridges and other odds and ends

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

A programming language for FPGAs.

一步一步写MIPS CPU

Tools for running FPGA vendor toolchains with Docker

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A Compiler for the Popr Language

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

Verilog SDRAM memory controller

Yet Another Tetris on FPGA Implementation

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Facilitates building open source tools for working with hardware description languages (HDLs)

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。