342 Open source projects that are alternatives of or similar to Spatial Lang

A mixed signal netlist language (pre-alpha)

Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

Homotopy theory in Coq.

A FPGA friendly 32 bit RISC-V CPU implementation

Regression test suite for Icarus Verilog.

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

CoreIR Symbolic Analyzer

A single-wire bi-directional chip-to-chip interface for FPGAs

FPGA 101 - Workshop materials

FPGA implementation of Cellular Neural Network (CNN)

A small 6502 system with MS BASIC in ROM

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

RTL, Cmodel, and testbench for NVDLA

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Mega CD for MiSTer

Sega Genesis for MiSTer

This is the base project for the Mojo. It should be used as the starting point for all projects.

A nicer HDL.

A MIPS CPU implemented in Verilog

Example designs showing different ways to use SymbiFlow toolchains.

High throughput JPEG decoder in Verilog for FPGA

Realtime VGA to ASCII Art converter

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

CDBUS Protocol and the IP Core for FPGA users

FuseSoC-based SoC for SweRV EH1

This is the main repository for all the examples for the book Practical UVM

A very primitive but hopefully self-educational CPU in Verilog

Code generation tool for configuration and status registers

A Video display simulator

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

FPGA-based C64 Accelerator / C65 like computer

A wishbone controlled scope for FPGA's

A low pin count sniffer for ICEStick - targeting TPM chips

FPGA-based RISC-V CPU+SoC.

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

GPGPU microprocessor architecture

Human Resource Machine - CPU Design #HRM

The Antikernel operating system project

FuseSoC standard core library

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

My solutions to Alteras example labs

This repository is used to release the Labs of Computer Architecture Course from USTC

Stuff from CTF contests

Ham Radio hat for Raspberry PI

Featherweight RISC-V implementation

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

冯爱民老师《计算机组成原理A》课程设计

IC design and development should be faster，simpler and more reliable

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Pano Logic G2 Reverse Engineering Project

Light-weight RISC-V RV32IMC microcontroller core.

Compact FPGA game console

Bitcoin miner for Xilinx FPGAs

A reimplementation of a tiny stack CPU