430 Open source projects that are alternatives of or similar to Verilog-Practice

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

PDP-6 Emulator

Sphinx Extension which generates various types of diagrams from Verilog code.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

MOS6581 SID chip emulator in SystemVerilog

react-native practice albums' project.

The repository is about 100+ python programming exercise problem discussed, explained, and solved in different ways

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Coding for food

Lattice iCE40: development platform for PlatformIO

Questions and solutions (in Java) for technical CS interview problems

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Collection of Linux Kernel Modules and PoC to discover, learn and practice Linux Kernel Development

COMPETITIVE PROGRAMMING PRACTICE QUESTIONS

My CodeWars solutions in Python.

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Facilitates building open source tools for working with hardware description languages (HDLs)

Standard Cell Library based Memory Compiler using FF/Latch cells

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

web application for team members to typing library

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Yet Another RISC-V Implementation

SpinalHDL - Cryptography libraries

An initiative to increase the visibility of open source opportunities within the Elixir community.

A deliberate practice framework to help you learn Ruby

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

NN on FPGA

Simple 3-stage pipeline RISC-V processor

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

This repository is for the first time contributors. Test and practice how to contribute

Data Structures & Algorithms - A Comprehensive Guide

FAST-9 Accelerator for Corner Detection

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

A list of the shortest tutorials ever.

A complete guide to start and improve in machine learning (ML), artificial intelligence (AI) in 2022 without ANY background in the field and stay up-to-date with the latest news and state-of-the-art techniques!

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Репозиторий практик факультета ИТиАБД направления Прикладной Информатики в Финансовом Университете при Правительстве РФ

Virtio implementation in SystemVerilog

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

A Hardware Construct Language

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

FPGA-based JPEG-LS image compressor.

One can follow to excel in coding if you are a noob!!

Sheet Music Creation, Groove Experimentation, and Practice Tool for drummers.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Virtual development board for HDL design

Programmable multichannel ADPCM decoder for FPGA

Trying to verify Verilog/VHDL designs with formal methods and tools

A programming language for FPGAs.

A Google Chrome extension which adds a timer to practice timed problem solving on codeforces

Cross EDA Abstraction and Automation

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

covers python basic to advance topics, practice questions, logical problems in python, web development using html, css, bootstrap, jquery, DOM, Django 🚀🚀. 💥 🌈

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Reads a state transition system and performs property checking

Javascript assignments, tasks and katas

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Generator of verilog description for FPGA MobileNet implementation