550 Open source projects that are alternatives of or similar to ZYNQ-NVDLA

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

mirror of https://git.elphel.com/Elphel/eddr3

Global Dark Mode for ALL apps on ANY platforms.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

PDP-6 Emulator

LicheeTang 蜂鸟E203 Core

Verilog Generator of Neural Net Digit Detector for FPGA

FPGA/hardware design of openwifi

Must-have verilog systemverilog modules

SpinalHDL - Cryptography libraries

Generator of verilog description for FPGA MobileNet implementation

i8080 precise replica in Verilog, based on reverse engineering of real die

Connectal is a framework for software-driven hardware development.

NN on FPGA

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Recipe for FPGA cooking

CHIP-8 console on FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

All open source file and project for OpenFPGAduino project

SHA-256 IP core for ZedBoard (Zynq SoC)

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Yet Another Tetris on FPGA Implementation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

A programming language for FPGAs.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

MOS6581 SID chip emulator in SystemVerilog

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A utility for Composing FPGA designs from Peripherals

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

GPGPU microprocessor architecture

A simple, basic, formally verified UART controller

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

FPGA-based JPEG-LS image compressor.

A Video display simulator

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Bus bridges and other odds and ends

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Small Processing Unit 32: A compact RV32I CPU written in Verilog

32-bit Superscalar RISC-V CPU

Notes on the Red Pitaya Open Source Instrument

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

Compact FPGA game console

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Cross EDA Abstraction and Automation

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

DMA source and sink blocks for Xilinx Zynq FPGAs

Docker Development Environment for SpinalHDL

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Lattice iCE40: development platform for PlatformIO

Virtio implementation in SystemVerilog

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

The Antikernel operating system project

FPGA-based RISC-V CPU+SoC.

Tools for running FPGA vendor toolchains with Docker

Programmable multichannel ADPCM decoder for FPGA