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All Programming Languages → tcl

Top 693 tcl open source projects

CUGR, VLSI Global Routing Tool Developed by CUHK

✭ 61

C++c python shell tcl CMake routing eda physical-design

Triple Modular Redundancy

✭ 16

Verilog tcl VHDL c shell assembly

153. flask-djcelery

An example project for configuring Djcelery with Flask application and dynamically changing tasks via REST API and through django admin

✭ 13

c tcl HTML perl ruby M4 flask-application django-admin flask-djcelery schedule-interval

a language where the programs are works of modern art (updated for OSX)

✭ 20

c Yacc tcl Roff shell Makefile

Perlin noise benchmark

✭ 77

lua rust c C#tcl java

simple tabbed text editor written in core Tcl/Tk

✭ 17

tcl editor text tcltk text-editor tk tabbed tedit tcl-tk

Z-EVES for linux. Probably the only place you can find it

✭ 17

python tcl c TeX Makefile emacs lisp linux formal-methods legacy-application z-eves z-notations

FOS - FPGA Operating System

✭ 49

VHDL c Coq Jupyter Notebook SystemVerilog tcl

159. vp awsfpga

Virtual Platform for AWS FPGA support

✭ 14

Verilog SystemVerilog c C++tcl Makefile

160. PlayStation MiSTer

PlayStation for MiSTer FPGA

✭ 180

VHDL Verilog SystemVerilog tcl

161. bitcoin mining

Simple test fpga bitcoin miner

✭ 20

Verilog shell python Batchfile tcl Stata

162. rygar-fpga

A FPGA core for the arcade game, Rygar (1986).

✭ 17

VHDL Verilog SystemVerilog c Coq tcl game fpga arcade mister rygar

163. Atari800 MiSTer

Atari 800XL/65XE/130XE for MiSTer

✭ 23

VHDL Verilog SystemVerilog c assembly tcl

164. XilinxBoardStore

No description, website, or topics provided.

✭ 117

python tcl shell

A central location for IxNetwork sample scripts and utilities. Please also visit http://openixia.com

✭ 41

python tcl perl ruby RobotFramework OpenEdge ABL

Testing Firmware for OpenPOWER systems

✭ 30

python shell tcl c testing boot testing-tools opal openpower testing-framework firmware-image

Implementation of an RSA VDF evaluator targeting FPGAs.

✭ 41

SystemVerilog tcl python C++Makefile Verilog

bind9, forked from git://git.debian.org/~lamont/bind9.git, plus DNS Dampening patch

✭ 14

c shell C++perl XSLT tcl

Vivado build system

✭ 40

tcl python Makefile shell

No description, website, or topics provided.

✭ 78

C++tcl Jupyter Notebook python c shell

171. PyQt4 locadora

PyQt4 - Locadora de Veículos

✭ 24

HTML python tcl c C++QML mvc pyqt4 sqlite3

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

✭ 111

C++c Makefile python tcl CMake

173. Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

✭ 16

Verilog tcl SystemVerilog Makefile shell javascript fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

174. TPU-Tensor-Processing-Unit

IC implementation of TPU

✭ 32

Verilog rust tcl Batchfile typescript shell

175. drakon.tech

Drakon.Tech is an IDE based on the DRAKON visual language

✭ 28

javascript lua emacs lisp HTML CSS tcl

The source code to the Voss II Hardware Verification Suite

✭ 19

Verilog c tcl Yacc haskell Makefile

Open, Modular, Deep Learning Accelerator

✭ 136

scala C++tcl c python Verilog machine-learning hardware tensor tvm vta

UFFS - Ultra low cost Flash File System

✭ 29

c tcl shell Makefile Bison C++

No description, website, or topics provided.

✭ 21

G-code Verilog HTML shell tcl SystemVerilog

180. rcs-db-ext

Database extension (runtimes)

✭ 18

python ruby c tcl NSIS HTML

181. MiSTer-Arcade-SEGASYS1

FPGA implementation of SEGA SYSTEM 1 arcade board

✭ 18

Verilog VHDL SystemVerilog Coq tcl Batchfile

The Integrated Data Viewer (IDV) from Unidata is a framework for analyzing and displaying geoscience data.

✭ 62

java HTML python tcl Inno Setup ruby

183. ps3mfw-builder-0.2.1-mod

modified version of toolboy's MFW-Builder

✭ 23

184. Xcode.app-strings

All the strings from Xcode's binaries

✭ 73

perl python shell ruby javascript tcl xcode reverse-engineering

An IRC server I wrote in 2004 for fun, using the Tcl language.

✭ 39

186. vivado-git

A git-friendly Vivado wrapper

✭ 111

A functional testing framework in object-oriented Tcl

✭ 23

tcl HTML XSLT shell

A fork of the OpenOCD project, used to build the xPack OpenOCD

✭ 39

c assembly HTML tcl perl Makefile

189. AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware

✭ 15

c Verilog tcl SystemVerilog python Makefile shell

190. UnityEditorTools

Unity编辑器工具

✭ 22

python tcl c HTML C#C++

191. OpenOCD-Nuvoton

Customized OpenOCD for Nuvoton devices

✭ 34

c HTML assembly tcl perl Makefile

192. projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

✭ 268

SystemVerilog tcl C++shell Makefile fpga

Python tools for Vivado Projects

✭ 65

python tcl VHDL shell

194. digital-flow

This is a tutorial on standard digital design flow

✭ 28

tcl Makefile Verilog synthesis synopsys logic-synthesis verilog-hdl timing-analysis

195. python-3parclient

This is a python client that talks to the HPE Alletra 9000 and HPE Primera and HPE 3PAR storage array via REST.

✭ 36

196. aes128-hdl

A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.

✭ 29

SystemVerilog VHDL shell tcl Stata

197. C64 MiSTer

No description, website, or topics provided.

✭ 73

SystemVerilog Verilog VHDL c tcl HTML Batchfile

Open CASCADE Technology (OCCT) is an open-source software development platform for 3D CAD, CAM, CAE. This is a clone of the official repository located on https://dev.opencascade.org/. Please use official development portal for registering issues and providing patches.

✭ 241

C++c tcl CMake GLSL Objective-C++cad cam cae opencascade occt 3d-cad

EBNF grammar of LLVM IR assembly.

✭ 55

200. dsi controller

MIPI DSI controller

✭ 37

HTML Verilog SystemVerilog tcl shell Makefile

151-200 of 693 tcl projects