773 Open source projects that are alternatives of or similar to async_fifo

Cross EDA Abstraction and Automation

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Global Dark Mode for ALL apps on ANY platforms.

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Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

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This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

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Bus bridges and other odds and ends

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Docker Development Environment for SpinalHDL

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

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Must-have verilog systemverilog modules

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

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【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

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A programming language for FPGAs.