1201 Open source projects that are alternatives of or similar to Cascade

GPGPU microprocessor architecture

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Connectal is a framework for software-driven hardware development.

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

All open source file and project for OpenFPGAduino project

Cross EDA Abstraction and Automation

Repository for basic (and not so basic) Verilog blocks with high re-use potential

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

NN on FPGA

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

PDP-6 Emulator

SpinalHDL - Cryptography libraries

Transient Array Radio Telescope

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

HW Design: A Functional Approach

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

mirror of https://git.elphel.com/Elphel/eddr3

A low cost FPGA development board for absolute newbies

Wishbone controlled I2C controllers

An open source library for image processing on FPGA.

Global Dark Mode for ALL apps on ANY platforms.

Robotic Application Processor

MOS6581 SID chip emulator in SystemVerilog

High-speed LaserDisc RF sampler

Generator of verilog description for FPGA MobileNet implementation

This repository contains iCEBreaker examples for Amaranth HDL.

FPGA-based JPEG-LS image compressor.

Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

Sphinx Extension which generates various types of diagrams from Verilog code.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Yet Another RISC-V Implementation

A full-speed device-side USB peripheral core written in Verilog.

A FPGA implementation of the NTP and NTS protocols

A configurable C++ generator of pipelined Verilog FFT cores

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

List of ideas for getting started with TimVideos projects

Video Game custom chips reverse-engineered from silicon

Scripts to build and use docker images including GHDL

Homebrew game for homebrew FPGA game console

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

A collection of phase locked loop (PLL) related projects

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Haskell library for hardware description

RISC-V CPU Core (RV32IM)

Various HDL (Verilog) IP Cores

🌱 Open source ecosystem for open FPGA boards

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

An abstraction library for interfacing EDA tools

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board