420 Open source projects that are alternatives of or similar to Chisel3

Chisel Things for OFDM

high-performance RTL simulator

Provides dot visualizations of chisel/firrtl circuits

Rocket Chip Generator

Quasar 2.0: Chisel equivalent of SweRV-EL2

A Hardware Construct Language

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

SpinalHDL - Cryptography libraries

Virtio implementation in SystemVerilog

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Recipe for FPGA cooking

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Facilitates building open source tools for working with hardware description languages (HDLs)

Scala based HDL

Various HDL (Verilog) IP Cores

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

FPGA-based JPEG-LS image compressor.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Haskell library for hardware description

Test suite designed to check compliance with the SystemVerilog standard.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Docker Development Environment for SpinalHDL

OpenROAD's unified application implementing an RTL-to-GDS Flow

Sphinx Extension which generates various types of diagrams from Verilog code.

FPGA-based RISC-V CPU+SoC.

Imitate SDcard using FPGAs.

Code generation tool for configuration and status registers

Test suite designed to check compliance with the SystemVerilog standard.

A utility for Composing FPGA designs from Peripherals

PicoRV32 - A Size-Optimized RISC-V CPU

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

RePlAce global placement tool

LicheeTang 蜂鸟E203 Core

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

this is an RTL Version of sb-admin2 Template, one of free template series in startbootstrap.com , (download remain file from startbootstrap.com)

A Verilog implementation of DisplayPort protocol for FPGAs

A convolutional neural network implemented in hardware (verilog)

Dreamcast HDMI

All open source file and project for OpenFPGAduino project

A simple, basic, formally verified UART controller

bootstrap 3 arabic

Bootstrap RTL Standard 3 and 4

Repurposing existing HDL tools to help writing better code

NES in Verilog

浙江大学计算机体系结构课程实验

Verilog module for calculation of FFT.

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

An FPGA based GDROM emulator for the Sega Dreamcast

A List of Free and Open Source Hardware Verification Tools and Frameworks

SystemVerilog language server